This invention relates to a semiconductor memory device, and more particularly to a multi-valued DRAM wherein multi-valued information is stored in a memory cell instead of binary information.
Memory capacity of the DRAM has been steadily increasing supported by the development of micro-technologies or hyper-integration-technologies. And, besides these structural exertions for microscopic integration, there have been also proposals to materialize a large scale DRAM by storing multi-valued information, quaternary information for example, in a memory cell.
As examples of the multi-valued DRAM, there are devices disclosed in Japanese patent applications laid open in Provisional Publications No. 95796/'87 (to be called a first example), No. 195896/'88 (to be called third example).
Outlines of these prior examples are briefly described in the following paragraphs.
In the first example, N-valued information is stored in a conventional type cell with a transistor and a capacitor as used usually in a DRAM for storing binary information. For reading-out the information, a stepping-up wave is supplied to a word-line and the differential potential detected on a bit-line is compared with one after another of N-1 reference potentials. For writing the information, stepping-down wave of N stages is recorded according to contents of the N registers storing the read-out information.
In the second example, for shortening a write time, there are provided N-1 resisters, N-2 capacitors having a same capacitance with the capacitance of a bit-line and charged according to contents of the resisters, and switching means which connect the N-2 capacitors to a bit-line for writing the information at once without using stepping-down wave.
In the third example, for shortening a read-out time, there is proposed a DRAM composed of multi-valued cells which operate on a new principle quite different from the first or the second example. The DRAM comprises a first bit-line pair, a second bit-line pair each bit-line of which has a half capacitance of a bit-line of the first bit-line pair, a first and a second sense amplifier for amplifying differential potentials detected between two bit-lines of the first and the second bit-line pair respectively, three pairs of dummy memory cells for generating reference potentials to be referred to by the sense amplifiers, and two pairs of auxiliary dummy cells for arranging capacitance differences.
A read-out operation of the third example is described theoretically.
First, by a selected memory cell, a differential potential is charged between two bit-lines of a first and second bit-line pairs connected with each other at the moment. Then the first bit-line pair is insulated from the second bit-line pair and the first sense amplifier amplifies the differential potential between the first bit-line pair sensing whether the differential potential corresponds to one of higher two values or lower two values of the four values storable in the memory cell referring to the first reference potential VR1 pre-charged by the first pair of dummy memory cells.
Then, the amplified potential is transferred to the second pair of dummy memory cells for generating a second referential potential VR2 together with a charge stored in the third pair of dummy memory cells when the differential potential corresponds to one of the higher two values, or a third reference potential VR3 when the differential potential corresponds to one of the lower two values. The reference potential VR2 or VR3 is referred to by the second sense amplifier for discriminating to which the differential potential remaining between the second bit-line pair corresponds of the four values storable in the memory cell.
The merits of the third example compared with the first or the second example consist in that it is composed of extended technologies of the ordinary binary DRAM and that no stepping wave is needed for write operation nor read-out operation, shortening both write and read-out times substantially.
The third example, however, has a problem that the read-out time remains still rather long compared with the ordinary binary DRAM because serial two discriminations by the sense amplifiers are necessary together with a transformation of the amplified potential between the pairs of dummy cells for charging the second referential potential.
Further, all of these three examples store N-valued information in a memory cell of a transistor and a capacitor, and so, have a problem of a decrease in operational margin because of the diminution of potential differences to be detected by sense amplifiers, resulting from the decrease of storable charge par bit in a memory cell with the reduction of sours voltages.
Suppose an example shown in FIG. 20 (A) composed of a bit-line B11 and a memory cell M1 with a transistor Q1 and a memory capacitor C1. Defining Cb as the capacitance of the bit-line B11, Cs as the capacitance of the memory capacitor C1, Vs as an initial potential of the node S1 of the memory cell M1, and Vh as a potential of the opposite electrode of the node S1, a following equation is obtained when the potential of the bit-line changes from Vi to Vx by stimulating a word-line WL1. EQU Cb.multidot.Vi+Cs(Vs-Vh)=Cb.multidot.Vx+Cs(Vx-Vh)
From the equation, Vx is represented as; EQU Vx=(Cb.multidot.Vi+Cs.multidot.Vs)/(Cb+Cs) (1)
Concrete examples of the potential Vx will be calculated, assuming that the source voltage Vcc is 5 V, Vi=2.5 V, Cb=350 fF and Cs=50 fF using the values described in the third example.
When the initial potential Vs of the node S1 has the maximum value of 5 V, Vx=2.81 V and when it has the minimum value of 0 V, Vx=2.19 V. For storing four valued information, for example, in a memory cell M1 with a transistor and a capacitor, two other initial values should be defined. When they are Vcc/3 (1.67 V) and 2 Vcc/3 (3.33 V), the corresponding values of Vx become 2.4 V and 2.6 V respectively.
FIG. 20 (B) illustrates the relation among the four values (a), (b), (c) and (d) of Vx thus obtained and the referential potentials VR1, VR2 and VR3 referred to by the sense amplifiers of the third prior example. The potential difference between VR1 and (b) or (c), VR2 and (a) or (b) and VR3 and (c) or (d) is about 100 mV. This is an example and the values of (b) and (c) of Vs or the values of VR1, VR2 and VR3 might be shifted, but no difference can be enlarged without reducing another difference. And, to reduce the source voltage Vcc, the differences must be reduced still more.